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COM'L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS
x Pin and function compatible with all PAL(R) 20V8 devices x Electrically erasable CMOS technology provides reconfigurable logic and full testability x High-speed CMOS technology
x x x x x x x x x x x
-- 5-ns propagation delay for "-5" version -- 7.5-ns propagation delay for "-7" version Direct plug-in replacement for a wide range of 24-pin PAL devices Programmable enable/disable control Outputs individually programmable as registered or combinatorial Peripheral Component Interconnect (PCI) compliant Preloadable output registers for testability Automatic register reset on power-up Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages Extensive third-party software and programmer support Fully tested for 100% programming and functional yields and high reliability Programmable output polarity 5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electricallyerasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices. Device logic is automatically configured according to the user's design specification. A design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming file based on Boolean or state equations. Design software also verifies the design and can provide test vectors for the finished device. Programming can be accomplished on standard PAL device programmers. The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically.
Publication# 16491 Amendment/0
Rev: E Issue Date: November 1998
The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
BLOCK DIAGRAM
I1 - I10
CLK/I0
10
Programmable AND Array 40 x 64
Input Mux.
MACRO MC0
MACRO MC1
MACRO MC2
MACRO MC3
MACRO MC4
MACRO MC5
MACRO MC6
MACRO MC7
Input Mux.
OE/I11 I12
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I13
16491E
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells (MC0-MC7). Each macrocell can be configured as a registered output, combinatorial output, combinatorial I/O, or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE20V8 are automatically configured from the user's design specification, which can be in a number of formats. The design specification is processed
2
PALCE20V8 Family
by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user's desired function. The user is given two design options with the PALCE20V8. First, it can be programmed as an emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL devices. The PAL device programmer manufacturer will supply device codes for the standard PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8 to the corresponding PAL device architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This option provides full utilization of the macrocells, allowing non-standard architectures to be built.
To Adjacent Macrocell
11 0X 10
OE VCC
11 10 00 01
SL0X SG1 11 0X D SL1X CLK Q Q 10 11 0X *SG1 *In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
16491E
I/OX
10
SL0X
From Adjacent Pin
Figure 1. PALCE20V8 Macrocell
PALCE20V8 Family
3
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, the buffer is always disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent I/O. The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell and SL1x sets the output as either active low or active high. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. These configurations are summarized in Table 1 and illustrated in Figure 2. If the PALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be used as data inputs. Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the flipflop. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALCE20V8 has three combinatorial output configurations: dedicated output in a nonregistered device, I/O in a non-registered device and I/O in a registered device. Dedicated Output in a Non-Registered Device The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.
Note: 1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC package.
4
PALCE20V8 Family
Dedicated Input in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The feedback signal is an adjacent I/O pin. Combinatorial I/O in a Non-Registered Device The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Combinatorial I/O in a Registered Device The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal.
Table 1. Macrocell Configuration
SG0 SG1 SL0X Cell Configuration Devices Emulated SG0 SG1 SL0X Cell Configuration Devices Emulated
Device Uses Registers 0 0 1 1 0 1 Registered Output Combinatorial I/O PAL20R8, 20R6, 20R4 PAL20R6, 20R4 1 1 1 0 0 1
Device Uses No Registers 0 1 1 Combinatorial Output Input Combinatorial I/O PAL20L2, 18L4, 16L6, 14L8 PAL20L2, 18L4, 16L6 PAL20L8
PALCE20V8 Family
5
OE
OE
D CLK
Q Q CLK
D
Q Q
a. Registered active Low
b. Registered active high
c. Combinatorial I/O active low VCC
d. Combinatorial I/O active high VCC
Note 1
Note 1
e. Combinatorial output active low
f. Combinatorial output active high
Note 2 Notes: 1. Feedback is not available on pins 18 (21) and 19 (23) in the combinatorial output mode. 2. This macrocell configuration is not available on pins 18 (21) and 19 (23). g. Dedicated input
16491E
Adjacent I/O Pin
Figure 2. Macrocell Configurations
6
PALCE20V8 Family
Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. Register Preload The register on the PALCE20V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit A security bit is provided on the PALCE20V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALCE20V8. It consists of 64 bits of programmable memory that can contain any user-defined data. The signature data is always available to the user independent of the security bit. Programming and Erasing The PALCE20V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability The PALCE20V8 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming and post-programming functional yields in the industry. Technology The high-speed PALCE20V8H is fabricated with Vantis' advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PCI Compliance PALCE20V8H devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE20V8H's predictable timing ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution.
PALCE20V8 Family 7
LOGIC DIAGRAM
0 34 78 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
CLK/I0 1 (2) I1 2 (3)
1 0
24 VCC (28) 23 (27) VCC
11 10 00 01
I 13
SG0
11 0X 10
0
SL0 7 SG1
D Q Q 10 11 0X 11 0X 10
22 I/O7 (26)
7
I2 3 (4)
SG0
SL07
11 0X 10
VCC
11 10 00 01
8
SL06 SG1
D Q Q 10 11 0X 11 0X 10
21 I/O6 (25)
15
I3 4 (5)
SG1
SL06
11 0X 10
VCC
11 10 00 01
16
SL05 SG1
D Q Q 10 11 0X 11 0X 10
20 I/O5 (24)
23
I4 5 (6)
SG1
SL05
11 0X 10
VCC
11 10 00 01
24
SL04 SG1
D Q Q 10 11 0X 11 0X 10
19 I/O4 (23)
31
I5 6 (7)
SG1
SL04
0
34
78
11 12 15 16 19 20 23 24 27 28
31 32 35 36 39
CLK OE
16491E
8
PALCE20V8 Family
LOGIC DIAGRAM (CONTINUED)
0 34 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
CLK OE
11 10 00 01
11 0X 10
VCC
32
SL03 SG1
D Q Q 10 11 0X 11 0X 10
18 I/O3 (21)
39
I6 7 (9)
SG1
SL0 3
11 0X 10
VCC
11 10 00 01
40
SL02 SG1
D Q Q 10 11 0X 11 0X 10
17 I/O2 (20)
47
I7 8 (10)
SG1
SL02
11 0X 10
VCC
11 10 00 01
48
SL01 SG1
D Q Q 10 11 0X 11 0X 10
16 I/O 1 (19)
55
I8 9 (11)
SG1
SL01
11 0X 10
VCC
11 10 00 01
56
SL00 SG1
D Q Q 10 11 0X 11 0X 10
15 I/O0 (18)
63
I 9 10 (12)
SG0
SL00
10 11 (13)
0 1
SG0
14 I12 (17) 13 OE/I11 (16)
0
34
78
11 12 15 16 19 20
23 24 27 28 31 32
35 36
39
16491E-4 (concluded)
PALCE20V8 Family
9
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to 75C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC (Static) ICC (Dynamic) Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current for -5 Supply Current for -7 and -10 Test Description IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 24 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) Outputs Open (IOUT = 0 mA), VIN = 0 V VCC = Max Outputs Open (IOUT = 0 mA), VCC = Max, f = 25 MHz -30 2.0 0.8 10 -100 10 -100 -150 125 115 Min 2.4 0.5 Max Unit V V V V A A A A mA mA mA
Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
10
PALCE20V8H-5/7/10 (Com'l)
CAPACITANCE
Parameter Symbol CIN COUT
1
Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V
Test Conditions VCC = 5.0 V, TA = 25C, f = 1 MHz
Typ 5 8
Unit pF pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol tPD tS tH tCO tSKEWR tWL tWH Maximum Frequency (Note 4) -5 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input or Feedback to Clock Hold Time Clock to Output Skew Between Registered Outputs (Note 3) LOW Clock Width HIGH External Feedback fMAX Internal Feedback (fCNT) No Feedback tPZX tPXZ tEA tER OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control 1/(tS+tCO) 1/(tS+tCF) (Note 5) 1/(tWH+tWL) 3 142.8 166 166 1 1 2 2 6 5 6 5 4 100 125 125 1 1 3 3 6 6 9 9 6 66.7 71.4 83.3 2 2 3 3 10 10 10 10 ns MHz MHz MHz ns ns ns ns 3 Min2 1 3 0 1 4 1 4 Max 5 Min2 3 5 0 1 5 1 6 -7 Max 7.5 Min2 3 7.5 0 3 7.5 1 -10 Max 10 Unit ns ns ns ns ns ns
1
Notes: 1. See "Switching Test Circuit" for test conditions. 2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALCE20V8H-5/7/10 (Com'l)
11
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to 75C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC (Dynamic) Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current for -10 Test Description IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 24 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) Outputs Open (IOUT = 0 mA), VCC = Max, f = 15 MHz (Note 4) -30 2.0 0.8 10 -100 10 -100 -150 55 Min 2.4 0.5 Max Unit V V V V A A A A mA mA
Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed worst case under test conditions. Refer to the ICC vs. frequency graph for typical measurements.
12
PALCE20V8Q-10 (Com'l)
CAPACITANCE
Parameter Symbol CIN COUT
1
Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V
Test Conditions VCC = 5.0 V, TA = 25C, f = 1 MHz
Typ 5 8
Unit pF pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol tPD tS tH tCO tWL tWH -10 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input or Feedback to Clock Hold Time Clock to Output LOW Clock Width HIGH External Feedback Maximum Frequency Internal Feedback (fCNT) (Note 3) No Feedback OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control 1/(tS+tCO) 1/(tS+tCF) (Note 4) 1/(tWH+tWL) 6 66.7 71.4 83.3 2 2 3 3 10 10 10 10 ns MHz MHz MHz ns ns ns ns Min2 3 7.5 0 3 6 7.5 Max 10 Unit ns ns ns ns ns
1
fMAX
tPZX tPXZ tEA tER
Notes: 1. See "Switching Test Circuit" for test conditions. 2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALCE20V8Q-10 (Com'l)
13
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to 75C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Description IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 24 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) Outputs Open (IOUT = 0 mA), VCC = Max, f = 15 MHz H Q -30 2.0 0.8 10 -100 10 -100 -150 90 mA 55 Min 2.4 0.5 Max Unit V V V V A A A A mA
Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
14
PALCE20V8H-15/25 Q-15/25 (Com'l)
CAPACITANCE
Parameter Symbol CIN COUT
1
Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V
Test Conditions VCC = 5.0 V, TA = 25C, f = 1 MHz
Typ 5 8
Unit pF pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol tPD tS tH tCO tWL tWH Maximum Frequency (Note 2) -15 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input or Feedback to Clock Hold Time Clock to Output LOW Clock Width HIGH External Feedback Internal Feedback (fCNT) No Feedback 1/(tS+tCO) 1/(tS+tCF) (Note 3) 1/(tWH+tWL) 8 45.5 50 62.5 15 15 15 15 12 37 40 41.6 20 20 25 25 ns MHz MHz MHz ns ns ns ns 8 12 0 10 12 Min Max 15 15 0 12 Min -25 Max 25 Unit ns ns ns ns ns
1
fMAX
tPZX tPXZ tEA tER
OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
Notes: 1. See "Switching Test Circuit" for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALCE20V8H-15/25 Q-15/25 (Com'l)
15
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Description IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 24 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.5 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.5 V, VCC = Max , VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) Outputs Open (IOUT = 0 mA), VCC = Max, f = 15 MHz H Q -30 2.0 0.8 10 -100 10 -100 -150 130 mA 65 Min 2.4 0.5 Max Unit V V V V A A A A mA
Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
16
PALCE20V8H-15/25 Q-20/25 (ind)
CAPACITANCE
Parameter Symbol CIN COUT
1
Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V
Test Conditions VCC = 5.0 V, TA = 25C, f = 1 MHz
Typ 5 8
Unit pF pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter Symbol tPD tS tH tCO tWL tWH Maximum Frequency (Note 2) -15 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input or Feedback to Clock Hold Time Clock to Output LOW Clock Width HIGH External Feedback fMAX Internal Feedback (fCNT) No Feedback tPZX tPXZ tEA tER OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control 1/(tS+tCO) 1/(tS+tCF) (Note 3) 1/(tWH+tWL) 8 45.5 50 62.5 15 15 15 15 10 41.6 45.4 50.0 18 18 18 18 12 37 40 41.6 20 20 25 25 8 12 0 10 10 Min Max 15 13 0 11 12 Min -20 Max 20 15 0 12 Min -25 Max 25
1
Unit ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
Notes: 1. See "Switching Test Circuit" for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALCE20V8H-15/25 Q-20/25 (ind)
17
SWITCHING WAVEFORMS
Input or Feedback Input or Feedback VT tPD Combinatorial Output VT Clock Registered Output
16491E-5 16491E-6
VT tS VT tCO VT tH
a. Combinatorial output
b. Registered output
Input tWH Clock tWL VT Output tER VOH - 0.5V VOL + 0.5V
VT tEA VT
16491E-8
c. Clock width
16491E-7
d. Input to output disable/enable
VT OE tPXZ Output VOH - 0.5V VOL + 0.5V tPZX VT
e. OE to output disable/enable
Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns to 5 ns typical.
16491E-9
18
PALCE20V8 Family
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V S1 R1 Output CL R2
16491E-10
Commercial Specification tPD, tCO tPZX, tEA S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 5 pF 50 pF 200 H-5: 200 390 CL R1 R2 Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
tPXZ, tER
PALCE20V8 Family
19
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25C
150
125
20V8H-5
100
20V8H-7 ICC (mA) 75 20V8H-10 20V8H-15/25
50 20V8Q-15/25
25
0 0 10 20 30 Frequency (MHz) 40 50
16491E-11
ICC vs. Frequency
The selected "typical" pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design.
20
PALCE20V8 Family
ENDURANCE CHARACTERISTICS
The PALCE20V8 is manufactured using Vantis' advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed--a feature which allows 100% testing at the factory.
Symbol tDR N Parameter Min Pattern Data Retention Time Max Operating Temperature Max Reprogramming Cycles Normal Programming Conditions 20 100 Years Cycles Test Conditions Max Storage Temperature Value 10 Unit Years
ROBUSTNESS FEATURES
The PALCE20V8X-X/5 have some unique features that make them extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns for the /5 versions.
PALCE20V8 Family
21
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE20V8H-7 AND PALCE20V8H-5
VCC VCC
> 50 k
ESD Protection and Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
VCC
VCC
> 50 k Provides ESD Protection and Clamping Preload Circuitry Feedback Input
16491E-12
Typical Output
Device PALCE20V8H-7 PALCE20V8H-5
Rev Letter A A
22
PALCE20V8 Family
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /4 VERSIONS
VCC
100 k VCC
0.5 kW
ESD Protection
Input
VCC
VCC
100 k
0.5 k
16491E-13
Preload Circuitry
Feedback Input
I/O Topside Marking:
Device PALCE20V8H-10 PALCE20V8H-15 PALCE20V8H-15 PALCE20V8H--25 PALCE20V8H-25 Rev Letter M L, M M M M Lattice/Vantis CMOS PLDs are marked on top of the package in the following manner: PALCEXXX Datecode (3 numbers) Lot ID (4 characters)--(Rev Letter) The Lot ID and Rev Letter are separated by two spaces.
PALCE20V8 Family
23
POWER-UP RESET The PALCE20V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: x The VCC rise must be monotonic.
x
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Symbol Parameter Descriptions Power-Up Reset Time Input or Feedback Setup Time See Switching Characteristics Clock Width LOW VCC tPR Registered Output tS Clock Min Max 1000 Unit ns
tPR tS tWL
4V Power
tWL
Figure 2. Power-Up Reset Waveform
16491E-15
24
PALCE20V8 Family
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc j a Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient 200 lfpm air j m a 400 lfpm air Thermal impedance, junction to ambient with air flow 600 lfpm air 800 lfpm air 50 47 38 36 PDID 19 73 61 53 PLCC 19 55 45 41 Unit C/W C/W C/W C/W C/W C/W
Plastic jc Considerations
The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE20V8 Family
25
CONNECTION DIAGRAMS
Top View
CLK/I0
SKINNYDIP
CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I13 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I12 OE/I11
16491E-16
PLCC
VCC I/O7 25 24 23 22 21 20 19 NC I13
I2 4 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11
I1 3
2
1
28 27 26 I/O6 I/O5 I/O4 GND/NC * I/O3 I/O2 I/O1
16491E-17
12 13 14 15 16 17 18 OE/I11 GND NC I9 I/O0 I10 I12
Note: Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK = Clock NC OE VCC = No Connect = Output Enable = Supply Voltage GND = Ground I I/O = Input = Input/Output
26
PALCE20V8 Family
ORDERING INFORMATION
Commercial and Industrial Products
Lattice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF FLIP-FLOPS OR OUTPUTS POWER H = Half Power (90-125 mA ICC) Q = Quarter Power (55 mA ICC) SPEED -5 = 5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD -25 = 25 ns tPD PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision (Same Algorithm as /4) CE 20 V 8 H -5 J C /5
OPERATING CONDITIONS C = Commercial (0C to +75C) I = Industrial (-40C to +85C) PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNY DIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
Valid Combinations PALCE20V8H-5 PALCE20V8H-7 PC, JC PALCE20V8H-10 PALCE20V8H-15 PALCE20V8Q-15 PALCE20V8Q-20 PALCE20V8H-25 PC, JC, PI, JI PALCE20V8Q-25 PC, JC, PI, JI PC, JC PI, JI /4 /4 JC /5
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations.
PALCE20V8 Family
27

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